Special issue on networks on chip

Every increase in capacity and complexity of integrated circuits has spurred the quest for ways to restrict the design space without sacrificing optimality. The microprocessor has done this in a very effective way, because it represents a general pattern to organize computation in hardware. The separation into a data-path with a number of optimized data manipulation units, a control machine that orchestrates the data manipulations, and the memory that stores the control and input, output and intermediate results, is effective and useful for every kind of application. Thus it provides an architectural pattern that implies an effective design methodology allowing to quickly implement any given algorithm. In fact, this architectural pattern is so general that the hardware implementation could be standardized and the architecture implementation is performed by storing a sequence of control instructions in memory, i.e. in software. The 1980s and 1990s saw a further steady increase of on-chip capacity and with it the investigation into a large variety of different variants of this basic architectural pattern leading to CISCs, RISCs, DSPs, ASIPs and a large number of customized ASIC architectures.